Generally, a circuit system integrated on a semiconductor chip is operated by receiving a supply voltage Vcc from the outside. A CMOS semiconductor chip usually employs a single voltage of 5V as the supply voltage Vcc. However, in CMOS semiconductor chip, although the supply voltage in the range of Vcc.+-.5% is given as the operating voltage, the operating voltage is substantially in the range of 4V to 6V.
Usually, the circuit system of CMOS semiconductor chip includes a signal delay circuit to achieve a special purpose of circuit. The signal delay circuit has a predetermined delay time by using a signal propagation delay time of the gate. For instance, a CMOS signal delay circuit using CMOS inverters is illustrated in FIG. 1A. This circuit comprises a first CMOS inverter DRV to drive a capacitive load CL according to an input signal VIN, and a second CMOS inverter BTT as a buffer amplifier for buffering and outputting a terminal voltage signal Vo of the capacitive load CL.
The terminal voltage signal Vo of the capacitive load CL has the delay characteristic according to the input signal VIN as shown in FIG. 1B. In detail, the capacitive load CL is discharged to ground voltage Vss or GND through pull-down NMOS transistor NM of the first CMOS inverter DRV, and is charged with the supply voltage Vcc through the pull-up PMOS transistor PM. Therefore, the delay time Td is determined by the voltage fall time Tf and the voltage rise time Tr according to the following equation: ##EQU1## Here, on the assumption that the threshold voltages VTN and VTP are approximately 0.2 Vcc and the current driving capabilities .beta. N and .beta. P of the MOS transistors NM and PM are equal to one another, the above equation (1) can be rewritten as the following equation: ##EQU2##
Referring to the above equation (2), it is known that the delay time Td is proportional to the capacitance of the capacitive load CL and inversely proportional to the supply voltage Vcc.
Accordingly, if the capacitance of the capacitive load CL is set to a fixed value, the delay time Td, as shown in FIG. 1C, varies according to the fluctuation of the supply voltage Vcc. In more detail, the delay time Td lengthens at low Vcc, and the delay time Td shortens at high Vcc.
But, since the conventional CMOS signal delay circuit keeps a constant load capacitance in the range of the operating voltage of the supply voltage Vcc, e.g., in 4V.about.6V, the operating speed of the overall circuit system is determined at low Vcc, so that the signal delay circuit becomes an impediment to the high operating speed. Also, since longer delay time is required at the high Vcc to prevent the occurrence of the race problem of the signal operating characteristic resulting from the difference between the delay characteristic of one part of the circuit and that of the other part of the circuit, the delay time becomes much longer to satisfy the above requirement, so that high speed operation of the overall chip is prevented.
Thus, a circuit having a predetermined delay time, which is independent of the change of the supply voltage, is earnestly required. If this requirement can be satisfied, the circuit delay at low Vcc becomes equal to that at high Vcc, so that the operating velocity of the overall chip (determined especially by the low Vcc) is kept fast. Accordingly, the performance of the circuit system of semiconductor chip can be greatly improved.